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| www..com PRELIMINARY PRELIMINARY CMOS SRAM KM641003C Document Title 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating). Revision History Rev. No. Rev. 0.0 Rev. 1.0 History Initial release with Preliminary. Release to Final Data Sheet. 1.1. Delete Preliminary. Preliminary CCPCCCRCELIMINARY Draft Data Aug. 5. 1998 Mar. 3. 1999 Remark Preliminary Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Revision 1.0 March 1999 www..com PRELIMINARY PRELIMINARY CMOS SRAM GENERAL DESCRIPTION KM641003C 256K x 4 Bit (with OE) High-Speed CMOS Static RAM FEATURES * Fast Access Time 12,15,20ns(Max.) * Low Power Dissipation Standby (TTL) : 30mA(Max.) (CMOS) : 5mA(Max.) Operating KM641003C - 12 : 70mA(Max.) KM641003C - 15 : 68mA(Max.) KM641003C - 20 : 65mA(Max.) * Single 5.0V10% Power Supply * TTL Compatible Inputs and Outputs * I/O Compatible with 3.3V Device * Fully Static Operation - No Clock or Refresh required * Three State Outputs * Center Power/Ground Pin Configuration * Standard Pin Configuration : KM641003CJ : 32-SOJ-400 Preliminary CCPCCCRCELIMINARY The KM641003C is a 1,048,576-bit high-speed Static Random Access Memory organized as 262,144 words by 4 bits. The KM641003C uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNGs advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM641003C is packaged in a 400 mil 32-pin plastic SOJ. PIN CONFIGURATION(Top View) N.C A0 A1 1 2 3 4 5 6 7 8 9 32 A17 31 A16 30 A15 29 A14 28 A13 27 OE FUNCTIONAL BLOCK DIAGRAM A2 A3 CS Clk Gen. A0 A1 A2 A3 A4 A5 A6 A7 A8 Pre-Charge Circuit I/O1 Vcc Vss 26 I/O4 SOJ 25 Vss 24 Vcc 23 I/O3 22 A12 21 A11 20 A10 19 18 A9 A8 I/O2 10 Row Select WE 11 12 13 14 15 Memory Array 512 Rows 512x4 Columns A4 A5 A6 A7 N.C 16 I/O1 ~ I/O4 17 N.C Data Cont. CLK Gen. I/O Circuit & Column Select PIN FUNCTION A9 A10 A11 A12 A13 A14 A15 A16 A17 Pin Name A0 - A17 Pin Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+5.0V) Ground No Connection CS WE OE WE CS OE I/O1 ~ I/O4 VCC VSS N.C -2- Revision 1.0 March 1999 www..com PRELIMINARY PRELIMINARY CMOS SRAM Symbol VIN, VOUT VCC Rating -0.5 to Vcc+0.5V -0.5 to 7.0 Unit V V W C C KM641003C ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Preliminary CCPCCCRCELIMINARY Pd 1 TSTG TA -65 to 150 0 to 70 * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70C) Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.5* Typ 5.0 0 Max 5.5 0 VCC+0.5** 0.8 Unit V V V V * VIL(Min) = -2.0V a.c (Pulse Width 8ns) for I 20mA. ** VIH(Max) = VCC + 2.0V a.c (Pulse Width 8ns) for I 20mA. DC AND OPERATING CHARACTERISTICS(TA=0 to 70C, Vcc=5.0V10%, unless otherwise specified) Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC Test Conditions VIN=VSS to VCC CS=VIH or OE=VIH or WE=VIL VOUT=VSS to VCC Min. Cycle, 100% Duty CS=VIL, VIN=VIH or VIL, IOUT=0mA Min. Cycle, CS=VIH f=0MHz, CS VCC-0.2V, VINVCC-0.2V or VIN0.2V IOL=8mA IOH=-4mA IOH1=-0.1mA 12ns 15ns 20ns Standby Current ISB ISB1 Output Low Voltage Level Output High Voltage Level VOL VOH VOH1* * VCC=5.0V5%, Temp.=25C. Min -2 -2 2.4 - Max 2 2 70 68 65 30 5 0.4 3.95 Unit A A mA mA V V V CAPACITANCE*(TA=25C, f=1.0MHz) Item Input/Output Capacitance Input Capacitance * Capacitance is sampled and not 100% tested. Symbol CI/O CIN Test Conditions VI/O=0V VIN=0V MIN - Max 8 6 Unit pF pF -3- Revision 1.0 March 1999 www..com PRELIMINARY PRELIMINARY CMOS SRAM KM641003C AC CHARACTERISTICS(TA=0 to 70C, VCC=5.0V10%, unless otherwise noted.) TEST CONDITIONS Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads Value Preliminary CCPCCCRCELIMINARY 3ns 0V to 3V 1.5V See below Output Loads(A) Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ RL = 50 +5.0V DOUT VL = 1.5V ZO = 50 30pF* DOUT 480 255 5pF* * Capacitive Load consists of all components of the test environment. * Including Scope and Jig Capacitance READ CYCLE Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Chip Selection to Power Up Time Chip Selection to Power DownTime Symbol tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tPU tPD KM641003C-12 Min 12 3 0 0 0 3 0 Max 12 12 6 6 6 12 KM641003C-15 Min 15 3 0 0 3 0 Max 15 15 7 7 7 15 KM641003C-20 Min 20 3 0 0 3 0 Max 20 20 9 9 9 20 Unit ns ns ns ns ns ns ns ns ns ns ns -4- Revision 1.0 March 1999 www..com PRELIMINARY PRELIMINARY CMOS SRAM Symbol tWC tCW tAS tAW tWP tWP1 tWR tWHZ tDW tDH tOW KM641003C-12 Min 12 8 0 8 8 12 0 0 6 0 3 Max KM641003C-15 Min Max KM641003C-20 Min Max 9 Unit ns ns ns ns ns ns ns ns ns ns ns KM641003C WRITE CYCLE Parameter Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width(OE High) Write Pulse Width(OE Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z 15 20 Preliminary CCPCCCRCELIMINARY 9 10 6 0 9 9 15 0 0 7 0 3 7 0 10 10 20 0 0 8 0 3 TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address tOH Data Out Previous Valid Data tAA Valid Data (Address Controlled, CS=OE=VIL, WE=VIH) tRC TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO tOE OE tOLZ tLZ(4,5) Valid Data ICC ISB tPU 50% tPD 50% tOH tHZ(3,4,5) CS tOHZ Data out VCC Current -5- Revision 1.0 March 1999 www..com PRELIMINARY PRELIMINARY CMOS SRAM NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. KM641003C Preliminary CCPCCCRCELIMINARY TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) tWC Address tAW OE tCW(3) CS tAS(4) WE tDW Data in High-Z tOHZ(6) Data out High-Z(8) Valid Data tDH tWP(2) tWR(5) TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in High-Z tWHZ(6) Data out High-Z(8) Valid Data tOW (10) (9) tWR(5) tWP1(2) tDH -6- Revision 1.0 March 1999 www..com PRELIMINARY PRELIMINARY CMOS SRAM KM641003C TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled) tWC Address Preliminary CCPCCCRCELIMINARY tAW tWR(5) tCW(3) tAS(4) tWP(2) CS WE tDW Data in tDH High-Z tLZ tWHZ(6) Valid Data High-Z Data out High-Z High-Z(8) NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. FUNCTIONAL DESCRIPTION CS H L L L * X means Dont Care. WE X H H L OE X* H L X Mode Not Select Output Disable Read Write I/O Pin High-Z High-Z DOUT DIN Supply Current ISB, ISB1 ICC ICC ICC -7- Revision 1.0 March 1999 www..com PRELIMINARY PRELIMINARY CMOS SRAM Units:millimeters/Inches KM641003C PACKAGE DIMENSIONS 32-SOJ-400 #32 Preliminary CCPCCCRCELIMINARY #17 10.16 0.400 11.18 0.12 0.440 0.005 9.40 0.25 0.370 0.010 0.20 #1 21.36 MAX 0.841 20.95 0.12 0.825 0.005 ( 1.30 ) 0.051 ( 1.30 ) 0.051 +0.10 -0.05 +0.004 0.017 -0.002 #16 0.69 MIN 0.027 0.008 +0.10 -0.05 +0.004 -0.002 3.76 MAX 0.148 0.10 MAX 0.004 ( 0.95 ) 0.0375 0.43 1.27 0.050 0.71 0.028 +0.10 -0.05 +0.004 -0.002 -8- Revision 1.0 March 1999 |
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